1 of 10 121907 features ? 10 years minimum data retention in the absence of external power ? data is automatically protected during power loss ? directly replaces 2k x 8 volatile static ram or eeprom ? unlimited write cycles ? low-power cmos ? jedec standard 24-pin dip package ? read and write access times as fast as 100 ns ? lithium energy source is electrically disconnected to retain freshness until power is applied for the first time ? full 10% v cc operating range (ds1220ad) ? optional 5% v cc operating range (ds1220ab) ? optional industrial temperature range of -40c to +85c, designated ind pin assignment 24-pin encapsulated package 720-mil extended pin description a0-a10 - address inputs dq0-dq7 - data in/data out ce - chip enable we - write enable oe - output enable v cc - power (+5v) gnd - ground description the ds1220ab and ds1220ad 16k n onvolatile srams are 16,384-bit, fu lly static, nonvolatile srams organized as 2048 words by 8 bits. each nv sram ha s a self-contained lithium energy source and control circuitry which constantly monitors v cc for an out-of-tolerance condition. when such a condition occurs, the lithium energy source is automatically switched on and write protection is unconditionally enabled to prevent data corrupti on. the nv srams can be used in place of existing 2k x 8 srams directly conforming to the popular bytewide 24-pin dip standard. the devices also match the pinout of the 2716 eprom and the 2816 eeprom, allowing direct substitution while enhancing performance. there is no limit on the number of write cycles that can be executed and no additional support circuitry is required for microprocessor interfacing. ds1220ab/ad 16k nonvolatile sram www.maxim-ic.com 14 vcc we 1 2 3 4 5 6 7 8 9 10 11 12 13 24 15 23 22 21 20 19 18 17 16 a7 a5 a3 a2 a1 a0 dq0 dq1 gnd dq2 a6 a4 a8 a9 oe a10 ce dq7 dq6 dq5 dq3 dq4
ds1220ab/ad 2 of 10 read mode the ds1220ab and ds1220ad exec ute a read cycle whenever we (write enable) is inactive (high) and ce (chip enable) and oe (output enable) are active (low). th e unique address sp ecified by the 11 address inputs (a0-a10) defines which of the 2048 byt es of data is to be accessed. valid data will be available to the eight data output drivers within t acc (access time) after the last address input signal is stable, providing that the ce and oe access times are also satisfied. if ce and oe access times are not satisfied, then data access must be measured from the later-occurring signal and the limiting parameter is either t co for ce or t oe for oe rather than address access. write mode the ds1220ab and ds1220ad execute a write cycle whenever the we and ce signals are active (low) after address inputs are stable. th e latter occurring falling edge of ce or we will determine the start of the write cycle. the write cycle is te rminated by the earlier rising edge of ce or we . all address inputs must be kept valid throughout the write cycle. we must return to the high state for a minimum recovery time (t wr ) before another cycle can be initiated. the oe control signal should be kept inactive (high) during write cycles to avoid bus contention. however, if the output drivers are enabled ( ce and oe active) then we will disable the outputs in t odw from its falling edge. data retention mode the ds1220ab provides full functional capability for v cc greater than 4.75 volts and write protects by 4.5v. the ds1220ad provides full functional capability for v cc greater than 4.5 volt s and write protects by 4.25v. data is maintained in the absence of v cc without any additional support circuitry. the nonvolatile static rams c onstantly monitor v cc . should the supply voltage decay, the nv srams automatically write protect themselves, all inputs become ?don?t care,? and all outputs become high impedance. as v cc falls below approximately 3.0 volts, a pow er switching circuit connects the lithium energy source to ram to retain data. during power-up, when v cc rises above approximately 3.0 volts, the power switching circuit connects external v cc to ram and disconnects th e lithium energy source. normal ram operation can resume after v cc exceeds 4.75 volts for the ds1220ab and 4.5 volts for the ds1220ad. freshness seal each ds1220 device is shipped from dallas semiconduc tor with its lithium energy source disconnected, guaranteeing full energy capacity. when v cc is first applied at a level of greater than v tp , the lithium energy source is enabled fo r battery backup operation.
ds1220ab/ad 3 of 10 absolute maxi mum ratings* voltage on any pin relative to ground -0.3v to +6.0v operating temperature 0c to 70c; -40c to +85c for ind parts storage temperature -40c to +70c; -40c to +85c for ind parts soldering temperature +260c for 10 seconds caution: do not reflow (wave or hand solder only) * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the ope ration sections of this specification is not implied. exposure to absolute maximum rating conditions for extended pe riods of time may affect reliability. recommended dc operatin g conditions (t a : see note 10) parameter symbol min typ max units notes ds1220ab power supply voltage v cc 4.75 5.0 5.25 v ds1220ad power supply voltage v cc 4.50 5.0 5.50 v logic 1 v ih 2.2 v cc v logic 0 v il 0.0 +0.8 v (t a : see note 10) (v cc =5v 5% for ds1220ab) dc electrical characteristics (v cc =5v 10% for ds1220ad) parameter symbol min typ max units notes input leakage current i il -1.0 +1.0 a i/o leakage current ce v ih v cc i io -1.0 +1.0 a output current @ 2.4v i oh -1.0 ma output current @ 0.4v i ol 2.0 ma standby current ce = 2.2v i ccs1 5.0 10.0 ma standby current ce = v cc -0.5v i ccs2 3.0 5.0 ma operating current (commercial) i cc01 75 ma operating current (industrial) i cco1 85 ma write protection voltage (ds1220ab) v tp 4.5 4.62 4.75 v write protection voltage (ds1220ad) v tp 4.25 4.37 4.5 v capacitance (t a =25c) parameter symbol min typ max units notes input capacitance c in 5 10 pf input/output capacitance c i/o 5 12 pf
ds1220ab/ad 4 of 10 (t a : see note 10) (v cc =5.0v 5% for ds1220ab) ac electrical characteristics (v cc =5.0v 10% for ds1220ad) ds1220ab-100 ds1220ad-100 ds1220ab-120 ds1220ad-120 parameter symbol min max min max units notes read cycle time t rc 100 120 ns access time t acc 100 120 ns oe to output valid t oe 50 60 ns ce to output valid t co 100 120 ns oe or ce to output active t coe 5 5 ns 5 output high z from deselection t od 35 35 ns 5 output hold from address change t oh 5 5 ns write cycle time t wc 100 120 ns write pulse width t wp 75 90 ns 3 address setup time t aw 0 0 ns write recovery time t wr1 t wr2 0 10 0 10 ns ns 12 13 output high from we t odw 35 35 ns 5 output active from we t oew 5 5 ns 4 data setup time t ds 40 50 ns 4 data hold time t dh1 t dh2 0 10 0 10 ns ns 12 13
ds1220ab/ad 5 of 10 ac electrical characteristics (cont?d) ds1220ab-150 ds1220ad-150 ds1220ab-200 ds1220ad-200 parameter symbol min max min max units notes read cycle time t rc 150 200 ns access time t acc 150 200 ns oe to output valid t oe 70 100 ns ce to output valid t co 150 200 ns oe or ce to output active t coe 5 5 ns 5 output high z from deselection t od 35 35 ns 5 output hold from address change t oh 5 5 ns write cycle time t wc 150 200 ns write pulse width t wp 100 150 ns 3 address setup time t aw 0 0 ns write recovery time t wr1 t wr2 0 10 0 10 ns ns 12 13 output high z from we t odw 35 35 ns 5 output active from we t oew 5 5 ns 4 data setup time t ds 60 50 ns 4 data hold time t dh1 t dh2 0 10 0 10 ns ns 12 13
ds1220ab/ad 6 of 10 read cycle see note 1 write cycle 1 see notes 2, 3, 4, 6, 7, 8 and 12 write cycle 2 see notes 2, 3, 4, 6, 7, 8 and 13
ds1220ab/ad 7 of 10 power-down/power-up condition see note 11 power-down/power-up timing (t a : see note 10) parameter symbol min typ max units notes v cc fail detect to ce and we inactive t pd 1.5 s 11 v cc slew from v tp to 0v t f 300 s v cc slew from 0v to v tp t r 300 s v cc valid to ce and we inactive t pu 2 ms v cc valid to end of write protection t rec 125 ms (t a =25c) parameter symbol min typ max units notes expected data retention time t dr 10 years 9 warning: under no circumstances are negative undershoots, of any amplitude, allowed when device is in the battery backup mode. notes: 1. we is high for a read cycle. 2. oe = v ih or v il . if oe = v ih during write cycle, the output buffers remain in a high-impedance state. 3. t wp is specified as the logical and of ce and we . t wp is measured from the latter of ce or ce going low to the earlier of ce or we going high. 4. t ds is measured from the earlier of ce or we going high. 5. these parameters are sampled with a 5 pf load and are not 100% tested. 6. if the ce low transition occurs simultaneously with or later than the we low transition, the output buffers remain in a high-impedance state during this period. 7. if the ce high transition occurs prior to or simultaneously with the we high transition, the output buffers remain in a high-impedance state during this period.
ds1220ab/ad 8 of 10 8. if we is low or the we low transition occurs prior to or simultaneously with the ce low transition, the output buffers remain in a high -impedance state during this period. 9. each ds1220ab and each ds1220ad has a built-in swit ch that disconnects the lithium source until v cc is first applied by the user. the expected t dr is defined as accumulative time in the absence of v cc starting from the time power is first applied by the user. this parameter is guaranteed by design and is not 100% tested. 10. all ac and dc electrical charac teristics are valid over the full operating temperature range. for commercial products, this range is 0c to 70c. for industrial product s (ind), this range is -40c to +85c. 11. in a power down condition the voltage on any pin may not exceed the voltage on v cc . 12. t wr1 , t dh1 are measured from we going high. 13. t wr2 , t dh2 are measured from ce going high. 14. ds1220 modules are recognized by u nderwriters laboratory (u.l. ? ) under file e99151. dc test conditions outputs open cycle = 200ns for operating current all voltages are referenced to ground ac test conditions output load: 100 pf + 1ttl gate input pulse levels: 0 - 3.0v timing measurement reference levels input: 1.5v output: 1.5v input pulse rise and fall times: 5ns ordering information part number temperature range supply tolerance pin/package speed grade ds1220ab-100 0c to +70c 5v 5% 24 / 720 emod 100ns ds1220ab-100+ 0c to +70c 5v 5% 24 / 720 emod 100ns ds1220ab-100ind -40c to +85c 5v 5% 24 / 720 emod 100ns ds1220ab-100ind+ -40c to +85c 5v 5% 24 / 720 emod 100ns ds1220ab-120 0c to +70c 5v 5% 24 / 720 emod 120ns ds1220ab-120+ 0c to +70c 5v 5% 24 / 720 emod 120ns ds1220ab-150 0c to +70c 5v 5% 24 / 720 emod 150ns ds1220ab-150+ 0c to +70c 5v 5% 24 / 720 emod 150ns ds1220ab-200 0c to +70c 5v 5% 24 / 720 emod 200ns ds1220ab-200+ 0c to +70c 5v 5% 24 / 720 emod 200ns ds1220ab-200ind -40c to +85c 5v 5% 24 / 720 emod 200ns ds1220ab-200ind+ -40c to +85c 5v 5% 24 / 720 emod 200ns ds1220ad-100 0c to +70c 5v 10% 24 / 720 emod 100ns ds1220ad-100+ 0c to +70c 5v 10% 24 / 720 emod 100ns DS1220AD-100IND -40c to +85c 5v 10% 24 / 720 emod 100ns DS1220AD-100IND+ -40c to +85c 5v 10% 24 / 720 emod 100ns ds1220ad-120 0c to +70c 5v 10% 24 / 720 emod 120ns ds1220ad-120+ 0c to +70c 5v 10% 24 / 720 emod 120ns ds1220ad-150 0c to +70c 5v 10% 24 / 720 emod 150ns ds1220ad-150+ 0c to +70c 5v 10% 24 / 720 emod 150ns ds1220ad-200 0c to +70c 5v 10% 24 / 720 emod 200ns ds1220ad-200+ 0c to +70c 5v 10% 24 / 720 emod 200ns ds1220ad-200ind -40c to +85c 5v 10% 24 / 720 emod 200ns ds1220ad-200ind+ -40c to +85c 5v 10% 24 / 720 emod 200ns + denotes lead-free/rohs-compliant product.
ds1220ab/ad 9 of 10 package information (for the latest package outline information, go to http://www.maxim-ic.com/dallaspackinfo .) package type document no. 24 dip 56-g0002-001
ds1220ab/ad 10 of 10 revision history revision date description pages changed 121907 added package information table. removed the dip module package drawing and dimension table. 9
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